As more circuits and functions are integrated into a single chip, a chip often has more power pins to supply the sufficient current for circuit operations. For different applications, the voltage levels of the high-state voltage sources VDD or VCC of the IC's are different. For example, the VDD in the typical 0.35-.mu.m CMOS technology with the gate-oxide thickness of 70 angstroms has been scaled down to 3.3V. However, the IC's with the gate-oxide thickness of 140 angstroms can be operated with a voltage of 5V. Therefore, the IC's in the system application may have the different power supplies with different voltage levels. Such IC's have been called as the mixed-voltage IC's.
Due to the difference of the voltage levels, the power lines and power pins in the IC's have to be separated. However, such a CMOS IC with separated power pins and separated power lines in the chip has been reported that the interface circuits are more sensitive to ESD (electrostatic discharge) damages, even if there are suitable ESD protection circuits placed around the input and output pads of the IC. The details are disclosed in the following references.
[1] N. Maene, J. Vandenbroeck, and L. Bempt, "On chip electrostatic discharge protections for inputs, outputs, and supplies of CMOS circuits," Proc. of EOS/ESD Symp., 1992, pp. 228-233.
[2] M. D. Ker and T. L. Yu, "ESD protection to overcome internal gate-oxide damage on digital-analog interface of mixed-mode CMOS IC's", Journal of Microelectronics and Reliability, vol. 36, no. 11/12, 1996, pp. 1727-1730.
[3] M. D. Ker, C. Y. Wu, T. Cheng, M. Wu, T. L. Yu, and A. Wang, "Whole-chip ESD protection for CMOS VLSI/ULSI with multiple power pins," Proc. of 1994 IEEE International Integrated Reliability Workshop, USA, Oct. 16-19, 1994, pp. 124-128.
[4] M.-D. Ker, C.-Y. Wu, H.-H. Chang, and T.-S. Wu, "Whole-chip ESD protection scheme for CMOS mixed-mode IC's in deep-submicron CMOS technology," Proc. of IEEE Custom Integrated Circuits Conference, Santa Clara, Calif., USA, May 5-8, 1997, pp. 31-34.
ESD stress may happen across any two pins of a CMOS IC. The ESD current may enter into the IC through an input or an output pin, and then go out the IC from another input or output pin. So, in the ESD testing standard, the pin-to-pin ESD stress has been specified as an ESD testing condition. The reference below introducing the ESD testing standard can be referenced.
[5] EOS/ESD Standard for ESD Sensitivity Testing, EOS/ESD Association, Inc., N.Y., 1993.
In the pin-to-pin ESD testing condition, the positive or negative ESD voltages are applied to a pin and the other input and output pins are grounded, but all pins of the voltage sources VDD and VSS are floating. This pin-to-pin ESD testing condition often causes some unexpected ESD damages on the internal circuits which beyond the protection of the input or output ESD protection circuits.
A schematic diagram of the pin-to-pin ESD testing is shown in FIG. 1. A positive ESD voltage is applied to an input pin or input pad 10i of circuit I with higher power supplies VDDH and VSSH, another output pin or output pad 12o of circuit II with lower power supplies VDDL and VSSL is relatively grounded. In such pin-to-pin ESD testing, VDDH, VSSH, VDDL, and VSSL are all floating. In FIG. 1, the CMOS IC has two circuits, circuit I and circuit II. Circuit I is supplied by the power supplies of VDDH and VSSH, whereas circuit II is supplied by the power supplies of VDDL and VSSL. VDDH is separated from the VDDL, and VSSH is separated from the VSSL. Circuit I and circuit II are connected by interface circuits 14 to transfer the signal message between circuit I and circuit II in the CMOS IC. As shown in FIG. 1, the ESD current I.sub.ESD is diverted into the VDDH power line through the diode Dpl in the input ESD protection circuit of circuit I. Since the output pad of circuit II is grounded, the initial voltage level on the VDDL and VSSL power lines is also relatively grounded. The ESD current may be conducted through circuit I into the VSSH power line. Therefore, the ESD stress voltage between the input pad 10i of circuit I and the output pad 12o of circuit II will become across between the power lines of VDDH/VSSH and the power lines of VDDL/VSSL. Such ESD voltage is therefore discharged through the interface circuits 14 and causes the ESD damages. Thus, the interface circuits between the separated power lines in a mixed-voltage CMOS IC are dangerous to such pin-to-pin ESD stress. The ESD protection circuits around the input pads and the output pads can not protect such unexpected damages located at the interface circuits 14 of a mixed-voltage CMOS with separated power pins and power lines.
A solution to ESD reliability in a CMOS IC is illustrated in FIG. 2. An extra ESD cell 16a is used to connect the separated VDDH and VDDL power lines and another extra ESD cell 16b is used to connect the separated VSSH and VSSL power lines. To protect the internal circuits of circuit I, an ESD clamp 18a is placed between the VDDH and VSSH power lines. To protect the internal circuits of circuit II, another ESD clamp 18b is placed between the VDDL and VSSL power lines. Thus the interface circuits 14 can be free of ESD damages during the pin-to-pin ESD stress.
To clearly explain the protection scheme of FIG. 2, the pin-to-pin ESD stress on such IC has been illustrated in FIG. 3a and FIG. 3b. In FIG. 3a, the positive ESD voltage is applied to an input pad 10i of circuit I and an output pad 12o of circuit II is relatively grounded. The ESD current is still diverted into the VDDH power line, but the ESD voltage on the VDDH power line can be discharged through the ESD cell 16a to the VDDL. On the other hand, the ESD voltage on the VDDH power line can be also discharged through the ESD cell 16b between the VSSH and VSSL power lines. Finally, the ESD current discharging paths are shown as dashed lines in FIG. 3a.
In FIG. 3b, the positive ESD voltage is applied to an output pad 12o of circuit II and an input pad 10i of circuit I is relatively grounded. The ESD current is still diverted into the VDDL power line, but the ESD voltage on the VDDL power line can be discharged through the ESD cell 16a to the VDDH. On the other hand, the ESD voltage on the VDDL power line can be also discharged through the ESD cell 16b between the VSSH and VSSL power lines. Finally, the ESD current is discharged through the ESD cells 16a and 16b through the input pad 10i to ground. Thus the interface circuits 14 can be protected against ESD damages.
From aforementioned ESD protection scheme, the ESD cell between the VDDH and VDDL has to provide the bi-directional current paths to bypass the ESD current from VDDH to VDDL and the ESD current from VDDL to VDDH in the ESD stress conditions. But such ESD cell also has to block the VDDH and VDDL power supplies due to the different voltage levels when the IC is in the normal operating conditions. Some prior arts had been designed by using the series diodes to connect the separated power lines in a CMOS IC, like the references listed below.
[6] S. Dabral, R. Aslett, and T. Maloney, "Designing on-chip power supply coupling diodes for ESD protection and noise immunity," in Proc. of EOS/ESD Symp., 1993, pp. 239-249.
[7] T. Maloney and S. Dabral, "Novel clamp circuits for IC power supply protection, " in Proc. of EOS/ESD Symp., 1995, pp. 1-12.
[8] H. Nguyen and J. Walker, "Electrostatic discharge protection system for mixed voltage application specific integrated circuit design," U.S. Pat. No. 5,616,943, April, 1997.
One typical design of such prior arts is shown in FIG. 4, where a plurality of diodes are connected from the VDDH to the VDDL of the CMOS IC. For a CMOS IC with a 5V VDDH and a 3V VDDL, four diodes 20a, 20b, 20c, and 20d have to be placed in the diode string to block the voltage difference between the VDDH and VDDL power lines. A diode 22a is also used to connect the separated power lines from the 3V VDDL to the 5V VDDH. Both the VSSH and VSSL are grounded when the IC is in the normal operating conditions. The ESD cell to connect the separated VSSH and VSSL power lines is also realized by the two diodes 24a and 26a in a back-to-back connection.
The diode string in FIG. 4 can be replaced by the NMOS string to connect the separated power lines of the CMOS IC. A prior art of such design is shown in FIG. 5 with four NMOS transistors Mn2a, Mn2b, Mn2c, Mn2d. The diodes can also be replaced by the PMOS Mp2a, Mp2b, Mp2c, Mp2d to perform the same function, as shown in FIG. 6. The number of the diode-connection NMOS or PMOS between the VDDH and VDDL power lines is dependent on the voltage difference between the VDDH and VDDL.
Another design to overcome such ESD issue is shown in FIG. 7, where a PMOS Mp1 with its parasitic drain-to-bulk diode Dp1 is used to connect the VDDH and VDDL power lines of the CMOS IC. In FIG. 8, the field-oxide device 28, or thick-oxide device as called, is used to connect the VDDH and VDDL, as illustrated in the above identified reference [8]. The similar designs by using the diodes, MOS's, BJT's, or field-oxide devices (FOD's) to connect the separated power lines in a CMOS IC is also reported in several US patents and papers as follows.
[9] J. Kuo, "ESD protection scheme," U.S. Pat. No. 5,196,981, March, 1993.
[10] J. Leach, "Method of forming an electrostatic discharge protection circuit," U.S. Pat. No. 5,290,724, March, 1994.
[11] W. Miller, "Electrostatic discharge protection for CMOS integrated circuits," U.S. Pat. No. 5,301,084, April, 1994.
[12] W. Reczek and H. Terletzki, "Integrated semiconductor circuit with ESD protection," U.S. Pat. No. 5,426,323, June, 1995.
[13] T. Maloney, "Electrostatic discharge protection circuits using biased and terminated PNP transistor chains," U.S. Pat. No. 5,530,612, June, 1996.
[14] S. Voldman, "Power sequence independent electrostatic discharge protection circuits," U.S. Pat. No. 5,610,791, March, 1997.
[15] S. Voldman, "Voltage regulator bypass circuit," U.S. Pat. No. 5,625,280, April, 1997.
[16] E. Worley, et al., "Sub-micron chip ESD protection schemes which avoid avalanching junctions," in Proc. of EOS/ESD Symp., 1995, pp. 13-20.
To protect the CMOS IC's against the ESD stresses, the ESD protection circuits are generally added to the input and output pins. To overcome the ESD damages caused by the VDD-to-VSS ESD stress, the ESD clamp device has been added between the VDD and VSS power lines of the IC products. But, to effectively protect the mixed-voltage CMOS IC with separated power lines, some suitable ESD cells have to be placed between the separated power lines of the mixed-voltage CMOS IC to avoid the ESD damage locating at the interface circuits between the circuits supplied by different power lines.